1. Field of the Invention
The present invention relates to a method for testing memories, and more particularly to a method for testing memories with seamless data input/output by interleaving seamless bank commands so as to detect a weakened memory.
2. Description of Related Art
While dynamic random access memories (DRAM) are manufactured by 0.2 μm process technology or an advanced manufacturing process, a power supply is lower than 3.3 volts, and a clock rate applied is higher than 133 megahertz, and the DRAM performance is then more and more sensitive to noise from external command signals, address signals, input data signals, and intrinsic noise raised from internal circuitry. For such consideration, DRAM designers have to carefully design memory circuits to provide correct data storage/access paths from each memory cell. On the other hand, DRAM manufacturing engineers must carefully control process conditions to guarantee target device/circuit performance. Even so, weakened memory cells still sometimes exist in DRAM chips and weakened data are probably stored. Thus, a challenge to test engineers is to provide a testing program to screen those memories and assist circuit designers to find critical data access paths and to cover device weakness.
A memory testing program is assembled by a pin condition setting, and a data access pattern. The pin condition setting includes setting of commanding pins, addressing pins and I/O pins. The data access pattern is used to define word-by-word data access paths and its corresponding operational clock rate. The pin condition setting, which includes true table setting and logic high/low voltage setting, is based on DRAM specification reference to data sheet. The data access pattern is, on the other hand, created by specific testing purposes. For instance, a one-dimensional row access pattern for accessing memory cells on a fixed word line (W/L) is applied to check word line continuity; and a one-dimensional column access pattern for accessing memory cells located on the same column is applied to check bit line (B/L) continuity. In the book “Testing Semiconductor Memory” written by A. J. van de Goor, published by John Wiley & Sons, there are traditional two-dimensional checkboards, GALPAT, sliding diagonals, butterfly patterns etc. for providing better fault coverage.
Usually, programming commands loops are used to carry out the access patterns mentioned above. For example, a memory has four banks (#0˜#3) are shown in FIGS. 5, 6A and 6B, a programmable cycling control command “Bank active—Write or Read—Bank pre-charge” is applied in the single bank (Bank #0), wherein the burst length in FIGS. 5, 6A and 6B is 4. In FIG. 5, while a “write” command is generated, data having four clock lengths are outputted from data input/output terminals (DQ). In FIGS. 6A and 6B, while a “read” command is generated, data in DQ respectively has two and three clock latency. This kind of cycling command is generally used to check basic functions of DRAM chips, however data in DQ are not inputted/outputted seamlessly.
With reference to FIGS. 7, 8A and 8B, those figures are similar to FIGS. 5, 6A and 6B, with a difference being that a programmable cycling command “Bank active—Write with auto pre-charge or Read with auto pre-charge” is applied in a single bank (Bank #0). This kind of loop is used to check functions of an auto pre-charge.
With reference to FIGS. 9 to 12, those figures disclose an interleave bank operation. Two banks interleave and four banks interleave operations are shown in FIGS. 9˜10 and FIGS. 11˜12 respectively Such repeated operations are capable to do seamless input/output (I/O) checks for examining I/O performance. Clearly, the operations shown in FIGS. 9 to 12 suffer larger noise due to more compact I/O operations than those shown in FIGS. 5 to 8. Although DQ in FIGS. 9 to 12 are inputted/outputted data seamlessly, control pins of memory still do not receive seamless controlling commands. Even four banks (Bank #0, #1, #2 and #3) receive initial “active” commands, the control pins still retain in a “wait” situation at 14th, 15th, 18th, 19th, 22nd, 23rd, 26th, 27th, clock cycles. Thus the commands shown in FIGS. 9 to 12 are not sufficient to detect weakened memory cells.
To overcome these shortcomings, the present invention tends to provide a method for testing a memory with seamless data input/output by interleaving seamless bank commands to mitigate and obviate the aforementioned problems.